The present disclosure relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device by forming a silicide layer on an interconnection after forming a liner.
As recent semiconductor devices are highly integrated and operate at high speeds, fine and multi-layer interconnections are used in the semiconductor devices. In addition, so as to reduce RC signal delays, copper is used as an interconnection material, and materials having a low dielectric constant (k) are used as insulation layer materials. Moreover, difficulties in metal patterning caused by design rule reduction have led to the development of a damascene process in which metal etching and insulation layer gap filling are not performed in an interconnection forming process.
In a damascene process, an etch stop layer and an interlayer insulation layer are formed on a substrate where lower interconnections are formed of copper; predetermined regions of the etch stop layer and the interlayer insulation layer are etched to form holes or trenches; and the holes or trenches are filled with a metal layer to form metal interconnections. At this time, a silicide layer may be formed on the lower interconnections, and the silicide layer may be nitrided to improve interconnection characteristics. The silicide layer may be formed by reaction with the lower interconnections. That is, the silicide layer may be formed by reaction between copper and a silicon source such as SiH4.
However, if copper and SiH4 make contact with each other and react with each other, the surface resistance of the lower interconnections may be varied to increase resistance such as via resistance or interconnection resistance after a device is completely fabricated. As a result, the operation of the device may be undesirably affected. For example, the device may not operate at a high speed.